This invention relates to a process for selectively etching a silicon dioxide layer deposited on a silicon nitride layer, and more particularly to a process for effectively and efficiently etching such silicon dioxide layer at a high etch rate and high selectivity of silicon dioxide with respect to silicon nitride, particularly in a multilayer structure.
It is known in the prior art that the manufacture of multilayer multilayer structures typically involves patterned etching of areas of the semiconductor surface which are not covered by a pattern of photoresist protective material. These etching techniques use liquid or wet etching materials, or dry etching with halogens or halogen-containing compounds, of certain layers of these devices. For example, one well known etching material is chlorine which can exist in the etching process as either chlorine gas or HCl, etc. Chlorine etches the semiconductor isotropically, i.e., in both a lateral and vertical direction. This results in an etched feature which has a line width which is smaller than the exposed resist image.
Etching of the multilayer structures can also be conducted in a gas phase using known techniques such as plasma etching, ion beam etching, and reactive ion etching. The use of gas plasma technology provides substantially anisotropic etching using gaseous ions, typically generated by an RF discharge. In gas plasma etching the requisite portion of the surface to be etched is removed by a chemical reaction between the gaseous ions and the subject surface. In the anisotropic process, etching takes place only or primarily in the vertical direction so that feature widths substantially match the photoresist pattern widths. Anisotropic etching is utilized when feature sizing after etching must be maintained within specific limits in order not to violate alignment tolerances or design rules. For example, in U.S. Pat. No. 4,734,157 an elemental silicon-containing layer, such as a layer of polysilicon or silicide, is etched anisotropically employing a gas plasma comprising a gaseous chlorofluorocarbon, capable of supplying CF.sub.x and chlorine ions, and ammonia. Profile control of a silicon layer is controlled by the use of this etching mode.
Higher density multilayer structures such as 64 and 256 Megabit DRAM will require an additional amount of alignment tolerance which can not be addressed by photolithography means. In such applications, an etch stop technology could be used to supply the desired tolerance. In an etch stop system an etch stop layer is deposited on underlying structures. The outer layer is deposited over the underlying etch stop layer through which the desired patterns will be defined. The etch stop layer will then be used to terminate the etch process once the outer layer has been completely removed in the desired pattern locations. Thus the etch stop layer acts to protected structures underlying the etch stop layer from damage due to the outer layer dry chemical etch. The process used to perform this etch must have three basic properties, namely, (1) a high outer layer etch rate which (2) produces substantially upright sidewalls and (3) has a high selectivity of the outer layer being etched down to the etch stop layer. The preferred etch stop material is silicon nitride because it's properties are well known and it is currently used for semiconductor fabrication. The preferred outer layer is silicon dioxide.
With respect to etching of a multilayer structure including a silicon dioxide layer on an underlying silicon nitride layer, a problem which occurs and which must be overcome is profile control. Prior art methods of obtaining high oxide to nitride selectivity rely on pure chemical etching (such as hydrofluoric acid). Profile control using this method produced structures that do not have vertical sidewalls. Dry etch processing usually produces a more vertical profile because of the ion bombardment aspect of the process. However, the dry etch process can produce a contact wall that slopes out from the bottom instead of being 90 if the wrong mix of process parameters are used. These parameters can include, but are not limited to, CF.sub.4, CHF.sub.3, RF Power, and pressure.
The same ion bombardment aspect of the dry etch process used to produce straight sidewalls has a very negative effect on oxide to nitride selectivity. High energy ions needed to etch both oxide and nitride do so by disassociating a chemical bond at the oxide and/or nitride surface. However the disassociation energy needed for nitride is less than that required for oxide. Hence the addition of CH.sub.2 F.sub.2 to offset the disassociation properties of nitride as compared to oxide. The CH.sub.2 F.sub.2 produces a polymer deposition on the nitride surface that acts to passivate the nitride surface and thereby reduce the dry etch removal rate. However, the silicon dioxide etch rate is sustained at a much higher rate than that of silicon nitride.
Here is a discussion of various prior art processes for etching silicon dioxide and/or silicon nitride. In U.S. Pat. No. 4,789,560 to Yen, for example, a fusion stop method is provided for forming silicon oxide during the fabrication of integrated circuit devices. A diffusion stop layer of thermal silicon oxide is formed during the fabrication of integrated circuit device prior to the deposition of the poly layer to be oxidized. The nitride isolates the substrate from diffused oxygen within the poly layer during oxidation, permitting a non-critical oxidation time.
U.S. Pat. No. 4,877,641 to Dory discloses a plasma CVD for forming silicon nitride or silicon dioxide films onto a substrate using a reactant gas including di-tert butylsilane and at least one other reactant gas.
U.S. Pat. No. 4,324,611 to Vogel et al. discloses a process and gas mixture for etching silicon dioxide and/or silicon nitride in a plasma environment in a planar reactor using a carbon fluorine gas comprising C.sub.2 F.sub.6, CF.sub.4, C.sub.3 F.sub.8, C.sub.4 F.sub.10, C.sub.4 F.sub.8, and combinations thereof.
U.S. Pat. No. 4,912,061 to Nasr discloses a method of forming a salicided self-aligned metal oxide multilayer structure using a disposable silicon nitride spacer.
U.S. Pat. No. 4,568,410 to Thornquist relates to the selective gaseous plasma etching with nitrogen fluoride and an oxygen source gas of silicon nitride in the presence of silicon oxide.
U.S. Pat. No. 3,479,237 to Bergh et al. discloses etching silicon oxide on silicon nitride using a hydrofluoric acid solution.
U.S. Pat. No. 4,971,655 to Stefano et al. discloses a method for protecting a refractory metal silicide during high-temperature processing using a dual-layer cap of silicon nitride on silicon dioxide.
U.S. Pat. No. 5,013,398 to Long et al. discloses a plasma etch process to anisotropically etch a sandwich structure of silicon dioxide, polycrystalline silicon and silicon dioxide "in situ", that is, in a single etch chamber.
U.S. Pat. No. 5,040,046 to Chhabra et al. discloses a process for forming silicon dioxide, or silicon nitride layers on selected substrates employing C.sub.4 H.sub.12 Si and an O.sub.2 source.
U.S. Pat. No. 5,013,692 to Ide et al. discloses a process for preparing film for a semiconductor memory device which comprises forming a silicon nitride film over a substrate by a chemical vapor deposition technique, oxidizing the surface of the silicon nitride film to form a silicon oxide layer over the film, and removing the silicon oxide layer by etching to form an improved silicon nitride film.
U.S. Pat. No. 4,244,752 to Henderson, Sr. et al. discloses a method of fabricating an integrated circuit wherein a silicon oxide-silicon nitride layer is formed on the surface of a silicon wafer.
U.S. Pat. No. 4,374,698 to Sanders, et al. relates to the etching of SiO.sub.2 or Si.sub.3 N.sub.4 with CF.sub.4, CF.sub.2 C.sub.12 or CF.sub.3 Br, and O.sub.2, while U.S. Pat. No. 4,581,101 to Senoue et al. etches the same materials with a fluorinated ether.
U.S. Pat. No. 5,043,790 to Butler uses upper and lower nitride layers in the formation of sealed self-aligned contacts. The upper non-conductive nitride layer is composed of silicon nitride which acts as an etch stop layer for an isotropic silicon dioxide wet etch. The lower nitride layer is a titanium nitride layer on a titanium silicide layer, both of which are conductive materials. The titanium nitride layer acts as an etch stop during an anisotropic dry etch of the silicon dioxide layer.
Current etch process technology for etching an SiO.sub.2 outer layer on an underlying Si.sub.3 N.sub.4 layer using a dry etcher, such as an RIE or MRIE etcher, cannot produce SiO.sub.2 -to-Si.sub.3 N.sub.4 selectivities above 3:1 with adequate profile and SiO.sub.2 etch rate characteristics. Therefore, a need exists for a process for etching a SiO.sub.2 layer on an underlying Si.sub.3 N.sub.4 layer, at a high SiO.sub.2 etch rate, and at a high selectivity of SiO.sub.2 with respect to the underlying Si.sub.3 N.sub.4, to form an etched multilayer structure at a controlled predetermined profile in which the sidewalls are substantially upright.